Semiconductor chips or wafers are used in many applications, including as integrated circuits and as flash memory for hand held computing devices, wireless telephones, and digital cameras. Regardless of the application, it is desirable that a semiconductor chip hold as many circuits or memory cells as possible per unit area. In this way, the size, weight, and energy consumption of devices that use semiconductor chips advantageously is minimized, while nevertheless improving the memory capacity and computing power of the devices.
In chips that hold integrated circuits, the individual circuit components are interconnected by conductive elements referred to as "interconnect lines". These interconnect lines are typically arranged in a multi-layered pattern that is deposited on a semiconductive substrate such as silicon. To insulate the interconnect lines from each other, insulative material is deposited between adjacent interconnect line layers.
With the above in mind, so-called 0.25 micron technology has been developed, in which the distance between adjacent layers of interconnect lines in an integrated circuit on a semiconductor chip is equal to or less than about three-eighths of a micron. With such a small spacing between interconnect lines, which have heights of about 1.1 microns, the size of the circuits on the chip can be reduced to result in the above-noted advantages.
Typically, each electrically conductive interconnect line is made of a "stack" of metal layers that typically includes a layer made of aluminum or aluminum alloy, and one or more other metal layers. The aluminum is deposited as a film over the substrate and is then lithographically patterned and chemically etched to form a desired pattern for the circuit's connector lines. Then, a process referred to as high density plasma (HDP) inter-layer dielectric (ILD) formation is used to fill the gaps between adjacent metal stacks with an electrically non-conductive material.
HDP ILD formation is preferred for 0.25.mu. technology over the older plasma enhanced chemical vapor deposition (PECVD) process. When ILD is deposited over and between the stacks, voids can form in the ILD between the stacks. Such void formation would reduce the insulation between adjacent stacks and thus lead to undesirable short circuits within the chip. In the PECVD process, to avoid ILD void formation it is necessary to sequentially deposit ILD and then etch away excess ILD, with repeat iterations being necessary to ensure that voids do not form in the ILD between the stacks. It happens that as the distance between adjacent stacks is decreased to the 0.375.mu. range, the problem of void formation is exacerbated and, hence, the shortcomings of the PECVD process magnified. On the other hand, in the HDP process the ILD material is deposited over and between the interconnect lines while simultaneously being sputtered away, thereby avoiding the formation of voids in the insulative material between the closely-spaced metal stacks while reducing fabrication time and, thus, increasing manufacturing throughput.
In HDP ILD formation, silane is used as the dielectric material. Silane has been preferred over tetraethoxy silane (TEOS) in 0.25.mu. semiconductor technology because it has a relatively high deposition rate, thus allowing for faster fabrication of the chips (and, hence, higher manufacturing throughput). Moreover, the process using silane is relatively easy to control with excellent quality. Also, silane is relatively inexpensive, compared to TEOS.
As recognized herein and confirmed by tests conducted by the present assignee, however, silane produces free hydrogen gas during fabrication, and it is to this problem that the present invention is addressed. More particularly, as recognized by the present invention free hydrogen gas is adsorbed by the aluminum, resulting in undesirable embrittlement of the aluminum. This is undesirable because, as the present invention understands, such embrittlement can promote the subsequent formation of voids in the aluminum that can be caused by mechanical stresses. These stresses arise largely because the thermal expansion coefficient of the mechanically constrained aluminum layer is different from the thermal expansion coefficient of the encapsulating oxide and the silicon substrate. When a void forms in a thin aluminum line, the current path through the line unfortunately is diverted, thereby adversely affecting the reliability of the chip.
Fortunately, the present invention recognizes that contrary to previous methods, TEOS can be used as the inter-layer dielectric in 0.25.mu. semiconductors. More particularly, the present invention recognizes that because the use of TEOS results in the production of relatively little or no free hydrogen, hydrogen embrittlement of aluminum in 0.25.mu. semiconductors consequently can be significantly reduced or indeed eliminated by using TEOS instead of silane, thereby improving 0.25.mu. chip reliability.